High-speed Pipeline Analog-to-Digital Converters (ADCs) often suffer from nonlinear distortion and structural mismatch, significantly limiting dynamic performance. Volterra-based behavioral modeling can uniformly characterize memory effects and nonlinear interactions, but their parameters grow exponentially with order and memory length, which causes redundancy, unstable identification and excessive complexity. Existing simplification methods, relying mostly on post-hoc pruning or sparsification, lack unified structural constraints and struggle to balance performance and complexity. This paper proposes a calibration method based on Order-Dependent Volterra and Dynamic Deviation Reduction (ODV-DDR). By introducing order-dependent memory allocation and dynamic deviation control in the structure generation stage, it systematically reduces parameter scale, improves the matrix condition number, and maintains the model’s ability to represent nonlinear distortions. Compared with existing methods, ODV-DDR achieves a better balance between calibration accuracy and model complexity, providing a generalizable modeling approach for efficient and stable nonlinear calibration. Verification results on a behavioral-level simulation platform show that ODV-DDR significantly improves the SFDR and SNDR under the condition of coexisting typical non-ideal errors. Its performance is close to that of the full Volterra model, while the parameter scale is significantly reduced. Therefore, this method demonstrates good practical value in balancing implementation complexity and performance, and provides a new approach for the digital calibration of high-speed ADC systems.

Nonlinear,Analog-to-Digital Converters,Calibration,Volterra,Dynamic Deviation Reduction