Aiming at the non-uniformity of channel length caused by two-layer lithography and high resistance of channel and JFET region in 4H-SiC VDMOS, a 650V 4H-SiC VDMOS with additional N-region is investigated. Sentaurus TCAD is utilized with the 4H-SiC material parameters included in the simulations to assess the threshold voltage V_th, on-state current I_DS, forward drain source blocking voltage V_DSS, maximum electric field in gate oxide E_OX,max, doping profile and dimension of the proposed device.The variation rules of key electrical parameters and corresponding process conditions are revealed and compared with the 650V conventional 4H-SiC VDMOS. Simulation results demonstrate that the threshold voltage V_th of 650V VDMOS with additional N-region is 0.2V higher than that of conventional VDMOS, and the specific on-state resistance R_DSon,sp of 650V VDMOS with additional N-region decreased by 0.8mΩ·cm² compared with the conventional VDMOS when the V_DSS and E_OX,max satisfy the design value.
 

4H-SiC；VDMOS；Additional N Region；JFET Resistance；Short channel