The parasitic effect induced by the interconnections in packaging brings about the dynamic current mismatch among paralleled dies, thus limiting the available capacity of the power module. In this paper, general analysis based on coupled parasitic network model is carried out to reveal the mechanism of layout-dominated dynamic current balancing in multichip silicon carbide (SiC) power modules. At first, according to the physical significance of parasitic parameters in power module, the coupled parasitic network model at switching transients is established to analyse the mechanism of dynamic current balancing. Next, for two different module layouts, parasitic parameters taking magnetic coupling into account are extracted from Q3D, including partial inductances and equivalent series resistances. Besides, on the basis of state space frequency-dependent model derived from the acquired parasitic parameters, the coupling simulation is conducted in SIMPLORER. Finally, the simulation data and switching waveforms of SiC MOSFETs are combined to verify the effectiveness of the proposed dynamic current balancing equations. As optimization guidelines, those can be satisfied by adjusting module layout to modify self and mutual partial inductances of the paralleled dies.

Dynamic current sharing,multichip power modules,package layout,SiC MOSFET,coupled parasitic network model