An accurate method for extracting the power loop parasitic inductance with high order polynomial fitting algorithm is proposed for the SiC MOSFET power module characterization. The power loop inductance distribution of the SiC MOSFET power module double pulse test platform is illustrated. The stray inductance is characterized using 5 sorts of approaches with integral method, differential method, least squares fitting method, sliding mean filtering algorithm and high order polynomial fitting algorithm at 400V/150A-570A. The experimental results using the existing 4 methods show relative errors more than 21.09nH from 8.17nH to 48.53nH compared to the tested inductance by impedance analyzer. Extracting inductance using high order polynomial fitting algorithm ranges from 30.42nH to 32.54nH at both low and high cureent, and the deviation is from 3.34nH to 5.50nH. Considering the inductance of the probe, the module contact terminal and the bus capacitor, the calculated results are consistent with the test result of 27.20nH. The parasitic inductance of 28.21nH simulated by ANSYS Q3D validates the accuracy of the proposed method. The fitted lines with the calculated stray inductance and di/dt match with the drain-to-source voltage of SiC MOSFET power module at both turn-on and turn-off transient.